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EMIF01-10005W5
EMI FILTER INCLUDING ESD PROTECTION
Application Specific Discretes A.S.D.TM
MAIN APPLICATIONS
Where EMI filtering in ESD sensitive equipment is required : Computers and printers Communication systems Mobile phones MCU Boards
DESCRIPTION
The EMIF01-10005W5 is a highly integrated array designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to 15 kV.
SOT323-5L
FUNCTIONAL DIAGRAM
BENEFITS
Cost-effectiveness compared to discrete solution EMI bi-directional low-pass filter High efficiency in ESD suppression. High flexibility in the design of high density boards Very low PCB space consuming : 4.2 mm2 typically High reliability offered by monolithic integration
I1 GND I2
RI/O = 100 CIN = 50pF
Filtering response
dB 0
O1
O2
COMPLIES WITH THE FOLLOWING STANDARD:
IEC 1000-4-2 15kV 8 kV (air discharge) (contact discharge)
ESD response to IEC1000-4-2 (16 kV air discharge)
-10
-20
f(MHz) -30 1 10 100 1000 2000
TM : ASD is trademark of STMicroelectronics.
May 1999 - Ed: 1
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EMIF01-10005W5
ABSOLUTE MAXIMUM RATINGS (Tamb = 25 C) Symbol VPP Tj Top Tstg TL Parameter and test conditions ESD discharge IEC1000-4-2, air discharge ESD discharge IEC1000-4-2, contact discharge Junction temperature Operating temperature range Storage temperature range Lead solder temperature (10 second duration) Value 16 9 150 -40 to + 85 -55 to +150 260 Unit kV C C C C
ELECTRICAL CHARACTERISTICS (Tamb = 25 C) Symbol VBR IRM VRM VCL Rd IPP RI/O CIN Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between Input and Output Input capacitance per line
slope : 1 / R d IPP VCL VBR VRM IRM IR
I
V
Symbol VBR IRM RI/O Rd CIN IR = 1 mA VRM = 3V
Test conditions
Min. 6
Typ. 7
Max. 8 1
Unit V A pF
80 Ipp = 10 A, tp = 2.5 s (see note 1) at 0V bias
100 1 50
120
Note 1 : to calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on pages 4 & 5
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TECHNICAL INFORMATION FREQUENCY BEHAVIOR
The EMIF01-10005W5 is firstly designed as an EMI/RFI filter. This low-pass filter is characterized by the following parameters: - Cut-off frequency - Insertion loss - High frequency rejection
Fig A1: EMIF01-10005W5 frequency response curve.
dB 0
-10
-20
f(MHz) -30 1 10 100 1000 2000
Figure A1 gives these parameters, in particular the signal rejection at the GSM frequency is about -24dB at 900MHz,
Fig A2: Measurement conditions
TRACKING GENERATOR
SPECTRUM ANALYSER
SMA
TEST BOARD
EMIF01
50 TG OUT
SMA RF IN
Vg
50
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EMIF01-10005W5
ESD PROTECTION
In addition to its filtering function, the EMIF01-10005W5 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at :
VCL = VBR + Rd.IPP
This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level.
Fig A3 : ESD clamping behavior
Rg R
ESD Surge
Rd Vg Vin Vbr
Rd Vout Vbr Rload
S1 EMIF01-10005W5
S2 Device to be protected
To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical resistance value Rd. By taking into account these following hypothesis : R>>Rd, RG>>Rd and Rload>>Rd, it gives these formulas:
Vin =
Rg.Vbr+Rd.Vg Rg R.Vbr+Rd.Vin R
Vout =
The results of the calculation done for VG=8kV, RG=330 (IEC1000-4-2 standard) and VBR=7V (typ.) give:
Vin = 31.2 V Vout = 7.3 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R.
Fig A4 : Measurement conditions
ESD SURGE 16kV Air Discharge
TEST BOARD
EMIF01
Vin
Vout
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The measurements shown here after illustrate very clearly (Fig. A5a) the high efficiency of the ESD protection : - no influence of the parasitic inductances on Vout stage - Vout clamping voltage very close to VBR
Fig A5 : Remaining voltage at both stages S1 (Vin) and S2 (Vout) during ESD surge
a) Positive surge
b) Negative surge
Please note that the EMIF01-10005W5 is not only acting for positive ESD surges but also for negative ones. For these kind of disturbances it clamps close to ground voltage as shown in Fig. A5b. NOTE: DYNAMIC RESISTANCE MEASUREMENT As the value of the dynamic resistance remains stable for a surge duration lower than 20s, the 2.5s rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd.
Fig A6 : Rd measurement current wave
I
IPP
t 2 s 2.5 s 2.5s duration measurement wave
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EMIF01-10005W5
CROSSTALK BEHAVIOR 1- Crosstalk phenomena Fig A7 : Crosstalk phenomena
RG1 line 1 VG1 VG2
VG1 RG2 line 2
RL1
VG2
RL2
VG2
VG1
DRIVERS
RECEIVERS
2- Digital Crosstalk Fig A8 : Digital crosstalk measurement
+5V 74HC04 Line 1 +5V VG1 Line 2 21 VG1 EMIF01 -10005W5 +5V 74HC04
Square Pulse Generator 5KHz
Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A9 shows that in such a condition signal from 0 to 5V and rise time of 3 ns, the impact on the disturbed line is less than 100mV peak to peak. No data disturbance was noted on the concerned line. The same results were obtained with falling edges.
Fig A9 : Digital crosstalk results
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3- Analog Crosstalk Fig A10 : Analog crosstalk measurement
TRACKING GENERATOR
SPECTRUM ANALYSER
SMA
TEST BOARD
EMIF01
50 TG OUT
SMA RF IN
Vg
50
Fig A11 : Typical analog crosstalk result
0 -20 -40 -60 -80 -100 dB
Figure A10 gives the measurement circuit for the analog application. In figure A11, the curve shows the effect of cell I/O1 on cell I/O2. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -43 dB.
1
10 F(MHz)
100
1,000
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4 - PSpice model Fig A12: PSpice model of one EMIF01 cell Fig A13: PSpice parameters
Dz 7 25p 100u 1000 10E-15 100p 1 0.3333 1 0.6 50n Df 1000 25p 100u 1000 1.016E-15 100p 1.0755 0.3333 1 0.6 50n Dr 1000 1p 100u 1000 10E-15 100p 0.6 0.3333 1m 0.6 1n
BV Cjo IBV IKF IS ISR N M RS VJ TT
Note This model is available for an ambient temperature of 27C
Fig. A14: PSpice simulation : IEC 1000-4-2 Contact Discharge response a) Positive surge
(V) 60 Vin 50 Vout 40 30 20 10 0 0 20 40 t(ns) 60 80 100
0 -10 -20 -30 -40 -50 -60 0 20 40 t(ns) 60 80 100 (V) Vin Vout
b) Negative surge
Fig A15: Comparison between PSpice simulation and measured frequency response
dB 0 Measured PSpice -10
-20
-30
1
10 F(MHz)
100
1,000
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EMIF01-10005W5
ORDER CODE
EMIF
EMI FILTER
01
-
100
05
W5
SOT323-5L package
TYPE
Input capacitance value /10
Series resistance value
Order code EMIF01-10005W5
Marking M12
Package SOT323-5L
Weight 5.4 mg
Base qty 3000
Delivery mode Tape & reel
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PACKAGE MECHANICAL DATA SOT323-5L DIMENSIONS REF.
A A2
Millimeters Min. Max. 1.1 0.1 1 0.3 0.18 2.2 1.35
Inches Min. 0.031 0 0.031 0.006 0.004 0.071 0.045 Max. 0.043 0.004 0.039 0.012 0.007 0.086 0.053
A1
A A1 A2
D e e
0.8 0 0.8 0.15 0.1 1.8 1.15
b c D E
H
E
e H
0.65 Typ. 1.8 0.1 2.4 0.4 0.071 0.004 0.094 0.016
Q1 c b
Q1
RECOMMENDED FOOTPRINT
0.3mm
Mechanical specifications Lead plating Tin-lead
1mm
Lead plating thickness
29mm
5m min. 25 m max. Sn / Pb (70% to 90% Sn) 100m max. Molded epoxy UL94V-0
Lead material Lead coplanarity
1mm
Body material Flammability
0.35mm
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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